1. Field of the Invention
The present invention relates to a circuit device and related method for mitigating electromagnetic interference (EMI), and more particularly to a circuit device and related method for mitigating EMI induced by signal transmission.
2. Description of the Prior Art
A liquid crystal display (LCD) is a flat panel display and has advantages of low radiation, light weight and low power consumption. Thus, the LCD is widely used in various information technology (IT) products, such as a notebook computer, a personal digital assistant (PDA), and a mobile phone. An active matrix thin film transistor (TFT) LCD is the mainstream in LCD families, especially in the large-size LCD family. In general, there is a driving system installed in the LCD, including a timing controller, source drivers and gate drivers. The source and gate drivers respectively control data lines and scan lines, which intersect to form a cell matrix. Each intersection is a cell including crystal display molecules and a TFT. In the driving system, the gate drivers are responsible for transmitting scan signals to gates of TFTs to turn on the TFTs on the panel. The source drivers are responsible for converting digital image data, sent by the timing controller, into analog voltage signals and outputting the voltage signals to sources of the TFTs. When the TFT receives the voltage signal, a corresponding liquid crystal molecule has a terminal whose voltage changes to equalize the drain voltage of the TFT, and thereby changes its own twist angle. The rate that light penetrates the liquid crystal molecule is accordingly changed and thus different colors can be displayed on the panel.
The timing controller mostly uses differential signaling (DS) interfaces to transfer data content to the source drivers. Common DS interfaces are multilevel differential signaling, reduced swing differential signaling (RSDS) and mini low voltage differential signaling (mini-LVDS) interfaces. The RSDS interface is characterized by two opposite current directions and an intensity level. In the multilevel differential signaling interface, the timing controller can transmit currents having different directions and multiple intensity levels. The currents generate voltages having different polarities and amplitudes on the terminal resistors of the source drivers, and thereby the source drivers can determine a type or logic state of the received voltage signal. Transmission interfacing architecture between the timing controller and the source drivers has two typical types: a bus signaling type, and a dedicated signaling type. Several source drivers share the same signaling lines to communicate with the timing controller in the bus signaling type, whereas each source driver uses independent signaling lines in the dedicated signaling type. The dedicated signaling architecture commonly has each source driver use one transistor-to-transistor (TTL) clock line and (k−1) data lines, or two DS clock lines and (k−2) data lines, where k is an integer greater than 2.
With advancements in LCD panel size, image resolution, and high data rates, the driving system needs to employ significantly large numbers of source drivers and transmission wires, which bring about non-negligible electromagnetic interference (EMI). As is well known in the art, the EMI is induced by current variation, and the EMI caused by one device negatively affects stabilization of signal transmission and processes of neighboring devices. During signal transmission, an instantaneous current having different variation rates and levels can generate different EMI degrees. The higher the variation level of the instantaneous current, the more strongly the EMI is induced.
For a driving system adopting a bus signaling architecture, since all of the source drivers jointly use a number of transmission lines, the timing controller has to simultaneously transmit interface display signals on those transmission lines, thereby causing a considerable instantaneous current. In general, the EMI is more severe in the bus signaling architecture than in the dedicated signaling architecture. Regarding a driving system adopting the dedicated signaling architecture, please refer to FIG. 1, which illustrates a schematic diagram of a driving system 10 according to the prior art. The driving system 10 includes a timing controller 100 and source drivers CD1-CD10. The timing controller 100 uses the multilevel differential signaling (DS) interface to transmit the interface display signals, which are embedded with display data content. On the other hand, each source driver receives the interface display signals via two independent DS line pairs, which are labeled by CDk_P/N, where k=1-10. The DS line pairs CDk_P/N have two DS line pairs: CDk_P and CDk_N. In addition, the DS line pair CDk_P includes DS lines CDk_0P and CDk_1P, whereas the DS line pair CDk_N includes DS lines CDk_0N and CDk_1N. In the driving system 10, the timing controller 100 transmits the interface display signals all with the same output phase on the DS line pairs CD1_P/N-CD10_P/N. As a result, all current transitions of the interface display signals occur at the same time, resulting in a significant instantaneous current variation. Please refer to FIG. 2, which illustrates a waveform diagram of the interface display signals of the DS line pairs CD1_P/N-CD10_P/N in the driving system 10. When the timing controller 100 transmits the in-phase interface display signals, as shown in FIG. 2, the current transitions on the DS line pairs CD1_P/N-CD10_P/N all happen at the same time. Assuming that an instantaneous current of level I is generated on each DS line pair, a total instantaneous current of level 10*I is generated, thereby causing severe EMI effect.
A solution of the prior art to mitigate the EMI is reducing the current levels in order to reduce the variation level of the instantaneous current. However, a large-size, high-resolution LCD has a great consumption of system currents due to a large number of signaling lines and a longer line length. Therefore, the solution has limited effectiveness.